1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various electrical test structures for evaluating semiconductor devices that employ high-k dielectrics and/or metal gate electrode structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
For many early device technology generations, the gate electrode structures of most transistor elements have been made from a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations. These high-k dielectric materials (k value greater than 10) may include, for example, hafnium oxide, zirconium oxide, etc. Illustrative metal gate electrode materials include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like. The HK/MG structures may be formed using so-called “gate-first” or “gate-last” techniques.
To make an integrated circuit on a semiconducting substrate, the various semiconductor devices, e.g., transistors, capacitors, etc., are electrically isolated from one another by so-called isolation structures. Currently, most sophisticated integrated circuit devices employ so-called shallow trench isolation (STI) structures. As the name implies, STI structures are made by forming a relatively shallow trench in the substrate and thereafter filling the trench with an insulating material, such as silicon dioxide. One technique used to form STI structures initially involves growing a pad oxide layer on the substrate and depositing a pad nitride layer on the pad oxide layer. Thereafter, using traditional photolithography and etching processes, the pad oxide layer and the pad nitride layer are patterned. Then, an etching process is performed to form trenches in the substrate for the STI structure using the patterned pad oxide layer and pad nitride layer as an etch mask. Thereafter, a deposition process is performed to overfill the trenches with an insulating material, such as silicon dioxide. A chemical mechanical polishing (CMP) process is then performed using the pad nitride layer as a polish-stop layer to remove the excess insulation material. Then, a subsequent deglazing (etching) process may be performed to insure that the insulating material is removed from the surface of the pad nitride layer. This deglaze process removes some of the STI structures.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. One problem that arises with current processing techniques is that, after the STI regions are formed, at least portions of the STI regions are exposed to many subsequent etching or cleaning processes that tend to consume, at least to some degree, portions of the STI structures subjected to such etching processes. As a result, the STI structures may have an uneven upper surface and may not perform their isolation function as intended, which may result in problems such as increased leakage currents, etc. Furthermore, since the erosions of the STI structures is not uniform across a die or a wafer, such structures may have differing heights, which can lead to problems in subsequent processing operations. For example, such height differences may lead to uneven surfaces on subsequently deposited layers of material which may require additional polishing time in an attempt to planarize the surface of such layer. Such additional polishing may lead to the formation of additional particle defects, which may reduce device yields.
One particular problem arising in connection with the manufacturing of HK/MG gates is that, when the gate structure passes over or near an STI structure, and gate encapsulation is compromised, the high-k insulating material and/or the metal in the gate electrode, e.g., titanium nitride, can also be attacked by many common cleaning chemicals employed in semiconductor manufacturing operations. For example, the high-k insulating materials and/or the metal portions of the gate electrode may be attacked by hydrogen peroxide that is present to at least some degree in cleaning agents such as ammonium hydroxide, sulphuric acid, hydrochloric acid, etc.
FIGS. 1A-1D are schematic drawings that will be referenced to further explain at least one common form of attack of high-k, metal gate structures. FIG. 1A is an illustrative example of a device 10 having an STI structure 14 formed in a semiconducting substrate 12 that has an upper surface 12S. Typically, after the pad oxide layer and pad nitride layer that are used in forming the STI structure 14 are removed, the upper surface 14S of the STI structure 14 (as initially formed) will be above the level of the surface 12S of the substrate 12. FIG. 1B depicts the STI structure 14 at a later point in fabrication wherein the STI structure 14 has been eroded by various cleaning operations which result in the formation of schematically depicted divots or notches 14D in the STI structure 14. The overall height of the STI structure is also typically reduced to some degree due to the consumption of the STI material during the various cleaning operations. FIG. 1C depicts an illustrative high-k, metal gate structure 16 that is formed above the STI structure 14. The gate structure 16 is comprised of a high-k insulating layer 16A (e.g., hafnium oxide), a metal layer 16B (e.g., titanium nitride) and a layer of polysilicon 16C. Also depicted in FIG. 1C are illustrative sidewall spacers 18 that are intended to be part of the encapsulation materials that protect the gate structure 16 from attack after it is formed. One problem that may arise when the gate structure 16 passes over or near an STI region is that there may be a breakdown in the encapsulation protection of the gate structure 16, as indicated in the region 20. When such encapsulation protection breaks down, the high-k insulation layer 16A and/or the metal layer 16B are subject to chemical attack which may create voids 22 under the polysilicon layer 16C.
FIG. 1D is a plan view of one illustrative example where the problems described above with respect to FIGS. 1A-1C may occur. FIG. 1D depicts a plurality of active regions 24A, 24B that are defined by an STI region 14. In the depicted embodiment, the illustrative gate structure 16 passes over the active region 24B and extends for a length 16E over the STI region 14. In some applications, the distance 16E may be on the order of 200-1000 nm. The portion of the gate structure 16 that is positioned over the active region 24B acts as a gate electrode structure for a transistor to be formed in and above the active region 24B. The gate structure 16 is provided with the extended length 16E to assist in patterning other gate structures (not shown). That is, better patterning definition is achieved when many closely spaced parallel lines are patterned instead of isolated lines.
In one example, it has been observed that the chemical attack of the high-k insulation layer 16A and/or the metal layer 16B occurs in the region 28 where the gate structure 16 passes near the active region 24A. In one example, the distance 26 between the edge of the active region 24A and the edge of the gate structure 16 may be less than 15 nm. After the chemical attack occurs in the region 28, it tends to propagate along the long axis of the gate structure 16 to the point where it may attack the portion of gate structure 16 that is positioned above the active region 24B and thereby degrade, if not destroy, the performance capabilities of the transistor device formed therein.
FIG. 2 depicts one illustrative example of a prior art test structure 30 for investigating attacks on high-k metal gate structures. The test structure 30 is generally comprised of a serpentine shaped body or line 34 that passes over or near various active regions 32 formed in a semiconducting substrate. The active regions 32 are bounded by STI regions 14. Conductive contacts 35 are formed on opposite ends of the line 34. The line 34 was generally comprised of a high-k gate insulation layer, a metal layer positioned above the gate insulation layer and a layer of non-silicided polysilicon positioned above the metal layer. Using this test structure 30, chemical attack of the high-k material or the metal layer of the line 34 could be determined by measuring the change in resistance level of the test structure, wherein an increase in the resistance level reflected a loss of some of the metal layer
The present disclosure is directed to various electrical test structures for evaluating semiconductor devices that employ high-k dielectrics and/or metal gate electrode structures that may at least reduce or eliminate one or more of the problems identified above.